Logic Diagram
TL F 9934 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Functional Description
The ’AC ’ACT169 uses edge-triggered J-K-type flip-flops
and have no constraints on changing the control or data
input signals in either state of the Clock The only require-
ment is that the various inputs attain the desired state at
least a setup time before the rising edge of the clock and
remain valid for the recommended hold time thereafter The
parallel load operation takes precedence over the other op-
erations as indicated in the Mode Select Table When PE is
LOW the data on the P0 – P3 inputs enters the flip-flops on
the next rising edge of the Clock In order for counting to
occur both CEP and CET must be LOW and PE must be
HIGH the U D input then determines the direction of count-
ing The Terminal Count (TC) output is normally HIGH and
goes LOW provided that CET is LOW when a counter
reaches zero in the Count Down mode or reaches 15 in the
Count Up mode The TC output state is not a function of the
Count Enable Parallel (CEP) input level If an illegal state
occurs the ’AC169 will return to the legitimate sequence
within two counts Since the TC signal is derived by decod-
ing the flip-flop states there exists the possibility of decod-
ing spikes on TC For this reason the use of TC as a clock
signal is not recommended (see logic equations below)
1) Count Enable e CEPCETPE
2) Up TC e Q0Q1Q2Q3(Up)CET
3) Down TC e Q0Q1Q2Q3(Down)CET
Mode Select Table
PE CEP CET U D
Action on Rising
Clock Edge
L X X X Load (Pn to Qn)
H L L H Count Up (Increment)
H L L L Count Down (Decrement)
H H X X No Change (Hold)
H X H X No Change (Hold)
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
State Diagrams
TL F 9934 – 6
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