Y Wide supply voltage range Y High noise immunity Y Low power TTL compatibility 3 0V to 15V 0 45 VDD (typ ) fan out of 2 driving 74L or 1 driving 74LS Applications Y Au.

and by connecting ‘‘Q’’ output to the data input for counter and toggle applications The logic level present at the ‘‘D’.

The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’ and ‘‘Q’’ outputs These d.

CD4013B

CD4013BM

CD4013BMS

CD4013A

CD40100B

CD40100BMS

CD40101B

CD40101BMS

CD40102B

CD40102BE

CD40102BMS

CD40103B

CD40103BE