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National Semiconductor Electronic Components Datasheet

CD4031BC Datasheet

64-Stage Static Shift Register

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February 1988
CD4031BM CD4031BC
64-Stage Static Shift Register
General Description
The CD4031BM CD4031BC is an integrated complemen-
tary MOS (CMOS) 64-stage fully static shift register Two
data inputs DATA IN and RECIRCULATE IN and a MODE
CONTROL input are provided Data at the DATA input
(when MODE CONTROL is low) or data at the RECIRCU-
LATE input (when MODE CONTROL is high) which meets
the setup and hold time requirements is entered into the
first stage of the register and is shifted one stage at each
positive transition of the CLOCK
Data output is available in both true and complement forms
from the 64th stage Both the DATA OUT (Q) AND DATA
OUT (Q) outputs are fully buffered
The CLOCK input of the CD4031BM CD4031BC is fully
buffered and present only a standard input load capaci-
tance However a DELAYED CLOCK OUTPUT (CLD) has
been provided to allow reduced clock drive fan-out and tran-
sition time requirements when cascading packages
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power TTL
compatibility
0 45 VDD (typ )
fan out of 2 driving 74L
or 1 driving 74LS
Y Fully static operation
Y Fully buffered clock input
DC to 8 MHz
VDD e 10V (typ )
5 pF (typ )
input capacitance
Y Single phase clocking requirements
Y Delayed clock output for reduced clock drive require-
ments
Y Fully buffered outputs
Y High current sinking capability
1 6 mA
Y Q output
VDD e 5V and 25 C
Logic and Connection Diagrams
Dual-In-Line Package
TL F 5962 – 1
Order Number CD4031B
Top View
C1995 National Semiconductor Corporation TL F 5962
TL F 5962 – 2
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

CD4031BC Datasheet

64-Stage Static Shift Register

No Preview Available !

Absolute Maximum Ratings (Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
b0 5V to a18V
b0 5V to VDD a0 5V
b65 C to a150 C
700 mW
500 mW
Lead Temp (TL) (Soldering 10 sec )
260 C
Recommended Operating
Conditions (Note 2)
Supply Voltage (VDD)
3V to 15V
Input Voltage (VIN)
0V to VDD
Operating Temperature Range (TA)
CD4031BM
CD4031BC
b55 C to a125 C
b40 C to a85 C
DC Electrical Characteristics (Note 2) CD4031BM
Symbol Parameter
Conditions
b55 C
a25 C
a125 C
Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V VIN e VDD or VSS
Current
VDD e 10V VIN e VDD or VSS
VDD e 15V VIN e VDD or VSS
5
0 01 5
150 mA
10
0 01 10
300 mA
20
0 02 20
600 mA
VOL Low Level Output VDD e 5V
l lVoltage
VDD e 10V VIH e VDD VIL e 0V IO k 1 mA
(VDD e 15V
0 05
0 05
0 05
0 0 05
0 0 05
0 0 05
0 05 V
0 05 V
0 05 V
( l lVOH
High Level Output
Voltage
VDD e 5V
VDD e 10V
VDD e 15V
4 95
VIH e VDD VIL e 0V IO k 1 mA 9 95
14 95
4 95
9 95
14 95
5
10
15
4 95
9 95
14 95
V
V
V
( l lVIL Low Level Input VDD e 5V VO e 0 5V or 4 5V
15
2 25 1 5
15 V
Voltage
VDD e 10V VO e 1 0V or 9 0V IO k 1 mA
30
45 30
30 V
VDD e 15V VO e 1 5V or 13 5V
40
6 75 4 0
40 V
( l lVIH High Level Input VDD e 5V VO e 0 5V or 4 5V
35
Voltage
VDD e 10V VO e 1 0V or 9 0V IO k 1 mA 7 0
VDD e 15V VO e 1 5V or 13 5V
11 0
3 5 2 75
70 55
11 0 8 25
35
70
11 0
V
V
V
(IOL
Low Level Output
Current Q Output
(Note 3)
VDD e 5V VO e 0 4V
VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
VIH e VDD
VIL e 0V
23 19 38
51 42 84
10 5 8 8 17
1 3 mA
2 8 mA
6 1 mA
(IOL
Low Level Output VDD e 5V VO e 0 4V
Current Q and CLD VDD e 10V VO e 0 5V
Outputs (Note 3) VD e 15V VO e 1 5V
VIH e VDD
VIL e 0V
0 64 0 51 0 88
1 6 1 3 2 25
42 34 88
0 36 mA
0 9 mA
2 4 mA
(IOH
High Level Output VDD e 5V VO e 4 6V
Current All Outputs VDD e 10V VO e 9 5V
(Note 3)
VDD e 15V VO e 13 5V
VIH e VDD
VIL e 0V
b0 64
b1 6
b4 2
b0 51 b0 88
b1 3 b2 25
b3 4 b8 8
b0 36
b0 9
b2 4
mA
mA
mA
IIN Input Current
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b0 1
01
b10b5 b0 1
10b5 0 1
b1 0 mA
1 0 mA
Truth Tables
Mode Control (Data Selection)
Mode
Control
Data
In
Recirculate
In
00
X
01
X
1X
0
1X
1
Data Into
First Stage
0
1
0
1
X e irrelevant NC e no change L e Low to High level transition
Each Stage
Dn
0
1
X
K e High to Low level transition
CL
L
L
K
Qn
0
1
NC
2


Part Number CD4031BC
Description 64-Stage Static Shift Register
Maker National Semiconductor
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CD4031BC Datasheet PDF






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