Datasheet4U Logo Datasheet4U.com

DM54LS125A - Quad TRI-STATE Buffers

Description

This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines wit

Features

  • Y Alternate Military Aerospace device (54LS125) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6387.
  • 1 Order Number 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125AM or DM74LS125AN See NS Package Number E20A J14A M14A N14A or W14B Function Table YeA Inputs A L H X H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level Hi-Z e TRI-STATE (Outputs are di.

📥 Download Datasheet

Datasheet preview – DM54LS125A

📁 Similar Datasheet

  • DM54LS47 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS48 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS49 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54L89A - 64-BIT READ/WRITE MEMORIES (ETC)
  • DM54141 - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM54155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (ETC)
  • DM5441A - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM5446A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5447A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5448 - BCD/7-Segment Decoder/Driver (MSI)
Other Datasheets by National Semiconductor
  • DM54LS10 - Triple 3-Input NAND Gates
  • DM54LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs
  • DM54LS11 - Triple 3-Input AND Gates
  • DM54LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS
  • DM54LS132 - NAND Gates
  • DM54LS138 - Decoders/Demultiplexers
  • DM54LS139 - Decoders/Demultiplexers
  • DM54LS14 - Hex Inverters with Schmitt Trigger Inputs

Full PDF Text Transcription

Click to expand full text
54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers June 1989 54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors When disabled both the output transistors are turned off presenting a high-impedance state to the bus line Thus the output will act neither as a significant load nor as a driver To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels the disable time is shorter than the enable time of th
Published: |