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FPD87310 Datasheet

Universal Interface XGA Panel Timing Controller with RSDS (Reduced Swing Differential Signaling) and FPD-Link

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PRELIMINARY
May 2000
FPD87310
Universal Interface XGA Panel Timing Controller with
RSDS(Reduced Swing Differential Signaling) and
FPD-Link
General Description
The FPD87310 Panel Timing Controller is an integrated
FPD-Link + RSDS + TFT-LCD Timing Controller. It resides
on the Flat Panel Display and provides the interface signal
routing and Timing Control between Graphics or Video Con-
trollers and a TFT-LCD system. FPD-Link, a low power, low
EMI (ElectroMagnetic Interference) interface is used be-
tween this Controller and the Host system.
A RSDS (Reduced Swing Differential Signaling) Column
Driver interface is used between the Timing Controller and
the Column Drivers.
Programmable, General Purpose Outputs provide Row and
Column Driver control. The FPD87310 is configured via
metal mask initialization value or an optional external serial
EEPROM. Reserved space in the EEPROM is available for
display identification information. The system can access the
EEPROM to read the display identification data or program
initialization values used by the FPD87310.
This single 9-bit+CLK differential bus conveys the 18 bits
color data for XGA panels at 130 Mb/s when using VESA 60
Hz standard timing.
Features
n RSDS (Reduced Swing Differential Signaling) Column
Driver bus for low power and reduced EMI
n Drives RSDS Column Drivers at 130 Mb/s with a 65
MHz clock
n 6- or 8-bit LVDS Video System Interface (FPD-Link)
n 10 General Purpose Outputs for Column/Row Drivers
n Optional EEPROM programming allows fine tuning in
development and production environments
n Selectable dual initialization value sets to share parts for
the different model panel module
n Ability to drive XGA/SVGA TFT-LCD Systems
n Narrow 9-bit+CLK differential Column Driver Bus
minimizes width of Source PCB
n CMOS circuitry operates from a 3.3V supply
n Supports Graphics Controllers with spread spectrum
interface featurefor lower EMI
System Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101077
DS101077-1
www.national.com


National Semiconductor Electronic Components Datasheet

FPD87310 Datasheet

Universal Interface XGA Panel Timing Controller with RSDS (Reduced Swing Differential Signaling) and FPD-Link

No Preview Available !

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Storage Temperature Range
(TSTG)
Lead Temperature (TL)
(Soldering 10 sec.)
4V
−0.3V to 4.0V
−0.3V to VDD +0.3V
−65˚C to +150˚C
260˚C
ESD Rating:
HBM
MM
Operating Conditions
Supply Voltage (VDD)
Operating Temp Range (TA)
Operating Frequency (fCLK)
2kV
200V
Min Max Units
3.0 3.6 V
0 70 ˚C
67 MHz
Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS VDD = 3.3V ± 0.3V, VSS = 0.0V (Unless otherwise specified).
Symbol
Parameter
Conditions
Min Typ
VOH Minimum High Level Output
Voltage
VDD = 3.3V, IOH = 8 mA
2.2
VOL Maximum Low Level Output
Voltage
VDD = 3.3V, IOL = 8 mA
VIH Minimum High Level Input Voltage
2.0
VIL Maximum Low Level Input Voltage
IIN Input Current
VIN = VSS to VDD
−10
IDD Supply Current
fCLK = 65 MHz, RPI = 13k, See
Figure 1
Max Units
V
0.8 V
V
0.8 V
10 µA
140 mA
FPD-Link (LVDS) RECEIVER INPUT (RxCLK+/−, RxIN[y]+/−; y = 0, 1, 2, 3)
Symbol
Parameter
Conditions
VIHLVDS
LVDS Input High Level Threshold VCMLVDS = +1.2V (Note 2)
Voltage
VILLVDS
VCMLVDS
LVDS Input Low Level Threshold
Voltage
LVDS Input Common Mode
Voltage Range
VCMLVDS = +1.2V (Note 2)
VDIFFLVDS = ± 100 mV (Note 2)
IIN LVDS Input Current
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
Min Typ Max Units
+100
mV
−100
mV
1.25
±10
±10
V
µA
µA
RSDS TRANSMITTER OUTPUT (RSCKP/N, RSx[y]P/N; x = R, G, B y = 0, 1, 2)
Symbol
VOHRSDS
VOLRSDS
VCMRSDS
Parameter
RSDS High Differential Output
Voltage
RSDS Low Differential Output
Voltage
RSDS Common Mode Output
Voltage
Conditions
VCMRSDS = +1.3V ± 5% (Note 3)
VCMRSDS = +1.3V ± 5% (Note 3)
VDIFFRSDS = ± 200 mV (Note 3)
Min
+150
Typ
+200
−200
1.3
Max
−150
Units
mV
mV
V
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: VCMLVDS = (VRxCLK+ + VRxCLK−)/2 or VCMLVDS = (VRxIN[y]+ + VRxIN[y]−)/2; y = 0, 1, 2, 3.
VDIFFLVDS = VRxCLK+ − VRxCLK− or VDIFFLVDS = VRxIN[y]+ − VRxIN[y]−; y = 0, 1, 2, 3
Note 3: VCMRSDS = (VRSCKP + VRSCKN)/2 or VCMRSDS = (VRSx[y]P + VRSx[y]N)/2; x = R, G, B y = 0, 1, 2
VDIFFRSDS = VRSCKP − VRSCKN or VDIFFRSDS = VRSx[y]P − VRSx[y]N; x = R, G, B y = 0, 1, 2
The Termination Resister for differential line between positive and negative output is 100.
Pin “PI” is connected to ground by 13.0 k. This parameter is Guaranteed by Design.
www.national.com
2


Part Number FPD87310
Description Universal Interface XGA Panel Timing Controller with RSDS (Reduced Swing Differential Signaling) and FPD-Link
Maker National Semiconductor
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