* n Reduced Swing Differential Signalling (RSDS™) digital bus reduces dynamic power, EMI and bus width from the timing controller n LVDS single pixel input interface system n Input clock range from 40 MHz to 85 MHz n Drives RSDS™ Column Drivers at 170 Mb/s with an 85 MHz clock (Max.) n Virtual 8 bit c
FPD87346 Datasheet (105.47 KB)
FPD87346
National Semiconductor
105.47 KB
Low dynamic power (svga) xga/wxga tft-lcd timing controller.
FPD87346 PRS Low EMI, Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller with Reduced Swing Differential Signaling (RSDS™) Outputs
PRELIMINA.
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