* N−Ch 0.50 A, 25 V
* RDS(ON) = 0.45 W @ VGS = 4.5 V
* RDS(ON) = 0.60 W @ VGS = 2.7 V
* P−Ch −0.41 A, −25 V
* RDS(ON) = 1.1 W @ VGS = −4.5 V
* RDS.

These dual N & P−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This de.

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