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FDG6321C Datasheet Dual N & P Channel Digital Fet

Manufacturer: Fairchild (now onsemi)

Overview: November 1998 FDG6321C Dual N & P Channel Digital FET General.

General Description

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS.

Key Features

  • N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 Ω @ VGS= 4.5V. RDS(ON) = 0.60 Ω @ VGS= 2.7 V. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 Ω @ VGS= -4.5V. RDS(ON) = 1.5 Ω @ VGS= -2.7V. Very small package outline SC70-6. Very low level gate drive requirements allowing direct operation in 3 V circuits(VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). SC70-6 SOT-23 SuperSOTTM-6 SOT-8 SO-8 SOIC-14 G2 D1 S2 1 6 .21 2 5 SC70-6 S1 D2 G1 3 4 Absolute Maximum Ratings Symbol VDSS VG.

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