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FDG6321C - Dual-Channel Digital FET

General Description

These dual N & P

effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology.

state resistance.

Key Features

  • N.
  • Ch 0.50 A, 25 V.
  • RDS(ON) = 0.45 W @ VGS = 4.5 V.
  • RDS(ON) = 0.60 W @ VGS = 2.7 V.
  • P.
  • Ch.
  • 0.41 A,.
  • 25 V.
  • RDS(ON) = 1.1 W @ VGS =.
  • 4.5 V.
  • RDS(ON) = 1.5 W @ VGS =.
  • 2.7 V.
  • Very Small Package Outline SC70.
  • 6.
  • Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V).
  • Gate.
  • Source Zener for ESD Ruggedness (>6 kV Human B.

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Datasheet Details

Part number FDG6321C
Manufacturer onsemi
File Size 229.09 KB
Description Dual-Channel Digital FET
Datasheet download datasheet FDG6321C Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Digital FET, Dual N & P Channel FDG6321C General Description These dual N & P−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially on low voltage replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. Features • N−Ch 0.50 A, 25 V ♦ RDS(ON) = 0.45 W @ VGS = 4.5 V ♦ RDS(ON) = 0.60 W @ VGS = 2.7 V • P−Ch −0.41 A, −25 V ♦ RDS(ON) = 1.1 W @ VGS = −4.5 V ♦ RDS(ON) = 1.5 W @ VGS = −2.