FDG6321C Datasheet and Specifications PDF

The FDG6321C is a Dual-Channel MOSFET.

Key Specifications

PackageSC
Mount TypeSurface Mount
Pins6
Height1.1 mm
Max Operating Temp150 °C
Min Operating Temp-55 °C
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Part NumberFDG6321C Datasheet
ManufacturerVBsemi
Overview FDG6321C FDG6321C Datasheet N- and P- Channel 20 V (D-S) MOSFET PRODUCT SUMMARY VDS (V) N-Channel 20 P-Channel - 20 RDS(on) (Ω) 0.090 at VGS = 4.5 V 0.110 at VGS = 2.5 V 0.130 .
* Halogen-free According to IEC 61249-2-21 Definition
* TrenchFET® Power MOSFETs: 1.8 V Rated
* Thermally Enhanced SC-70 Package
* Fast Switching
* Compliant to RoHS Directive 2002/95/EC APPLICATIONS
* Load Switch for Portable Devices D1 S2 G2 G1 S1 N-Channel D2 P-Channel ABSOLUTE MAXIMUM RAT.
Part NumberFDG6321C Datasheet
DescriptionDual-Channel Digital FET
Manufactureronsemi
Overview These dual N & P−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially.
* N
*Ch 0.50 A, 25 V
* RDS(ON) = 0.45 W @ VGS = 4.5 V
* RDS(ON) = 0.60 W @ VGS = 2.7 V
* P
*Ch
*0.41 A,
*25 V
* RDS(ON) = 1.1 W @ VGS =
*4.5 V
* RDS(ON) = 1.5 W @ VGS =
*2.7 V
* Very Small Package Outline SC70
*6
* Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th.
Part NumberFDG6321C Datasheet
DescriptionDual N & P Channel Digital FET
ManufacturerFairchild Semiconductor
Overview These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especia. N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 Ω @ VGS= 4.5V. RDS(ON) = 0.60 Ω @ VGS= 2.7 V. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 Ω @ VGS= -4.5V. RDS(ON) = 1.5 Ω @ VGS= -2.7V. Very small package outline SC70-6. Very low level gate drive requirements allowing direct operation in 3 V circuits(VGS(th) < 1.5 V). Gate-S.

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