MC100LVEL39 chip equivalent, clock generation chip.
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SOIC−20 WB DW SUFFIX CASE 751D
MARKING DIAGRAM* 20
100LVEL39 AWLYYWWG
1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package .
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The .
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devi.
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