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MTB15N06V Datasheet

Power Field Effect Transistor

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MTB15N06V
Designer’sData Sheet
TMOS V
Power Field Effect
Transistor
D2PAK for Surface Mount
NChannel EnhancementMode Silicon
Gate
TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50 and 60
volt TMOS devices. Just as with our TMOS EFET designs, TMOS V
is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed switching
applications in power supplies, converters and power motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors
Features Common to TMOS V and TMOS EFETs
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape
& Reel, Add T4 Suffix to Part Number
http://onsemi.com
TMOS POWER FET
15 AMPERES, 60 VOLTS
RDS(on) = 0.12 W
D2PAK
CASE 418B02,
Style 2
D
G
TM
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 3
1
Publication Order Number:
MTB15N06V/D


  ON Semiconductor Electronic Components Datasheet  

MTB15N06V Datasheet

Power Field Effect Transistor

No Preview Available !

MTB15N06V
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
DrainGate Voltage (RGS = 1.0 MΩ)
GateSource Voltage — Continuous
GateSource Voltage — NonRepetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
60 Vdc
60 Vdc
± 20 Vdc
± 25 Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse DraintoSource Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
ID
ID
IDM
PD
TJ, Tstg
EAS
15
8.7
45
55
0.37
3.0
55 to 175
113
Adc
Apk
Watts
W/°C
Watts
°C
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
2.73 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
http://onsemi.com
2


Part Number MTB15N06V
Description Power Field Effect Transistor
Maker ON Semiconductor
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