zero delay clock buffer.
http://onsemi.com MARKING DIAGRAMS*
8 1 SOIC−8 D SUFFIX CASE 751 1 8 XXXX ALYW G
8 8 1 TSSOP−8 DT SUFFIX CASE 948J XXX ALYWG G 1
* 15 MHz to 133 MHz Operating Range.
requiring zero input−output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it.
Pin # Pin Name Description
1 2 3 4 5 6 7 8
REF (Note1) CLK2 (Note 2) CLK1 (Note 2) GND CLK3 (Note 2) VDD CLK4 (Note 2) CLKOUT (Note 2)
Input reference frequency, 5 V tolerant input. Buffered clock output. Buffered clock output. Ground. Buffered cl.
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