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  ON Semiconductor Electronic Components Datasheet  

NB4L7210 Datasheet

2.5V/3.3V Differential 2x10 Crosspoint Clock Driver

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NB4L7210 pdf
NB4L7210
2.5V/3.3V Differential 2x10
Crosspoint Clock Driver
with SDI Programmable
Output Selects
The NB4L7210 is a Clock input crosspoint fanout distribution
device selecting between one of two input clocks on each of the 10
differential output pairs. A 10 Bit Serial Data Interface programs each
output MUX to asynchronously select either Input clock.
CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or
LVDS signal levels and incorporate an internal 50 ohms on die
termination resistors. SCLK, SDATA, and SLOAD input can accept
single ended LVPECL, CML, LVCMOS, LVTTL signals levels.
SCLK and SDATA inputs operate up to 20 MHz. SLOAD input
loads and latches the output select data. The SDATAOUT pin permits
cascading multiple devices. Outputs are optimized for minimal
output−to−output skew and low jitter.
Features
Typical Input Clock Frequency > 2 GHz
200 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Output to Output Skew 150 ps
Additive RMS Phase Jitter of 0.2 ps
Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
Differential LVPECL Output Level (Typ 700 mV Peak−to−Peak)
Low Profile 8x8 mm, 52 QFN Package
10GE WAN: 155.52 MHz / 622.08 MHz
10GE LAN: 161.1328 MHz
These are Pb−Free Devices*
www.onsemi.com
1 52
QFN52
MN SUFFIX
CASE 485M
MARKING
DIAGRAM*
52
1
NB4L
7210
AWLYYWWG
NB4L7210
A
WL
YY
WW
G
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK0
CLK0
CLK0b
VTCLK0b
Q0
Q0b
Q1
Q1b
VTCLK1
CLK1
CLK1b
VTCLK1b
VCC
VEE
SCLK
SDATA
SLOAD
Q8
Q8b
Q9
Q9b
SDATAOUT
Figure 1. Functional Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1
Publication Order Number:
NB4L7210/D


  ON Semiconductor Electronic Components Datasheet  

NB4L7210 Datasheet

2.5V/3.3V Differential 2x10 Crosspoint Clock Driver

No Preview Available !

NB4L7210 pdf
NB4L7210
52 51 50 49 48 47 46 45 44 43 42 41 40
Exposed Pad (EP)
GND
SLOAD
VTCLK0
1
2
3
CLK0
CLK0
VTCLK0
4
5
6
GND 7
VTCLK1 8
CLK1 9
CLK1 10
VTCLK1 11
SDATA 12
GND 13
NB4L7210
39 VCC3
38 Q3
37 Q3
36 VCC4
35 Q4
34 Q4
33 GND
32 Q5
31 Q5
30 VCC5
29 Q6
28 Q6
27 VCC6
14 15 16 17 18 19 20 21 22 23 24 25 26
Table 1. PIN DESCRIPTION
Figure 2. Pin Configuration (Top View)
Pin Name I/O
Description
1, 7, 13, 25, 26, 33,
40, 41
GND
Supply
Negative Supply pins must be all externally connected to a power
supply to guarantee proper operation.
2
SLOAD
LVCMOS, LVTTL Serial Load and Latch control input pin. Defaults LOW when float-
ing open.
3, 6, 8, 11
VTCLK0, VTCLK0,
VTCLK1, VTCLK1
Termination−
Internal 50 Ohms Termination Resistor connection Pins. In the
differential configuration when the input termination pins are con-
nected to the common termination voltage.
4, 9
CLK0, CLK1
Differential LVPECL, CLOCK Input (TRUE). If no signal is applied then the device may
CML, or LVDS
be susceptible to self oscillation.
5, 10
CLK0, CLK1
Differential LVPECL, CLOCK Input (INVERT). If no signal is applied then the device
CML, or LVDS
may be susceptible to self oscillation.
12
SDATA
LVCMOS, LVTTL Serial Data input pin (for BITS 0:9, a “0” selects CLK1, “1” selects
CLK 0). Defaults LOW when floating open.
14
SCLK
LVCMOS, LVTTL Serial Load Clock input pin. Defaults LOW when floating open.
15, 16, 19, 22, 27,
30, 36, 39, 44, 47,
50, 51
VCC, VCC9, VCC8,
VCC7, VCC6, VCC5,
VCC4, VCC3, VCC2,
VCC1, VCC0
Supply
Positive Supply pins must be all externally connected to a power
supply to guarantee proper operation.
17, 20, 23, 28, 31,
34, 37, 42, 45, 48
Q[9−0]
LVPECL
Output (INVERT)
18, 21, 24, 29, 32,
35, 38, 43, 46, 49
Q[9−0]
LVPECL
Output (TRUE)
52
SDATAOUT
LVCMOS, LVTTL Serial Data output pin for cascade
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bot-
tom (see case drawing) must be attached to a sufficient heat−
sinking conduit for proper thermal operation and must be connec-
ted to GND.
www.onsemi.com
2


Part Number NB4L7210
Description 2.5V/3.3V Differential 2x10 Crosspoint Clock Driver
Maker ON Semiconductor
Total Page 11 Pages
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