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  ON Semiconductor Electronic Components Datasheet  

NB6L14S Datasheet

2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator

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NB6L14S
2.5 V 1:4 AnyLevel]
Differential Input to LVDS
Fanout Buffer/Translator
The NB6L14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevel differential input signals: LVPECL, CML, LVDS, or
HSCL. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6L14S has a wide input common mode range from
GND + 50 mV to VCC 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6L14S is ideal for translating
a variety of differential or singleended Clock or Data signals to
350 mV typical LVDS output levels.
The NB6L14S is the 2.5 V version of the NB6N14S and is offered in
a small 3 mm x 3 mm 16QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
The NB6L14S is a member of the ECLinPS MAXfamily of high
performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Single Power Supply; VCC = 2.5 $ 5%
VREF_AC Reference Output
These are PbFree Devices
Device DDJ = 10 ps
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
IN
50 W
50 W
EN
(LVTTL/CMOS)
VREFAC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2011
October, 2011 Rev. 2
1
Publication Order Number:
NB6L14S/D


  ON Semiconductor Electronic Components Datasheet  

NB6L14S Datasheet

2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator

No Preview Available !

NB6L14S
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q1 1
Q1 2
Q2 3
Q2 4
NB6L14S
12 IN
11 VT
10 VREFAC
9 IN
5 678
Q3 Q3 VCC EN
Figure 3. NB6L14S Pinout, 16pin QFN (Top View)
Table 1. TRUTH TABLE
IN IN EN Q
01 1 0
10 1 1
xx
0 0 (Note 1)
1. On next transition of the input signal (IN).
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1 Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3 Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6 Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7 VCC
Positive Supply Voltage.
8 EN LVTTL / LVCMOS Input Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 26. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10 VREFAC
LVPECL Output
The VREFAC reference output can only be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, VREFAC should be connected to the VT pin and bypassed to ground
with a 0.01 mF capacitor.
11 VT
LVPECL Output
Internal 100 W Centertapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13 GND
Negative Supply Voltage.
14 VCC
15 Q0
LVDS Output
Positive Supply Voltage.
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16 Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
http://onsemi.com
2


Part Number NB6L14S
Description 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator
Maker ON Semiconductor
Total Page 11 Pages
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