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NCP5210 - PWM Dual Buck and Linear DDR Power Controller

Description

Description VDDQ error amplifier compensation node.

Features

  • include, soft.
  • start circuitry, undervoltage monitoring of 5VDUAL and BOOT voltage, and thermal shutdown. The device is housed in a thermal enhanced space.
  • saving QFN.
  • 20 package. Features.
  • Incorporates Synchronous PWM Buck Controllers for VDDQ and VMCH.
  • Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A.
  • All External Power MOSFETs are N.
  • Channel.
  • Adjustable VDDQ and VMCH by External Dividers.
  • VTT Tracks at Ha.

📥 Download Datasheet

Datasheet Details

Part number NCP5210
Manufacturer onsemi
File Size 238.11 KB
Description PWM Dual Buck and Linear DDR Power Controller
Datasheet download datasheet NCP5210 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NCP5210 3−in−1 PWM Dual Buck and Linear DDR Power Controller The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage. This IC contains two synchronous PWM buck controller for driving four external N−Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current. Protective features include, soft−start circuitry, undervoltage monitoring of 5VDUAL and BOOT voltage, and thermal shutdown.
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