The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8.
The CMOS memory has equal access and cycle times.
Inputs are fully TTL-compatible.
Key Features
High Speed Address-To-Match - 8 ns Maximum Access Time
High-Speed Read-Access Time.
8/10/12/15/20/25 ns (Commercial).
15/20/25 ns (Military)
Open Drain MATCH Output Reset Function
8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles
P4C174
HIGH SPEED 8K X 8 CACHE TAGE STATIC RAM
Data Retention at 2V for Battery Backup Operation
Advanced CMOS Technology Low Power Operation Package Styles Available.
Full PDF Text Transcription for P4C174 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
P4C174. For precise diagrams, and layout, please refer to the original PDF.
FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time High-Speed Read-Access Time – 8/10/12/15/20/25 ns (Commercial) – 15/20/25 ns (Military) Open Drain MATCH O...
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2/15/20/25 ns (Commercial) – 15/20/25 ns (Military) Open Drain MATCH Output Reset Function 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles P4C174 HIGH SPEED 8K X 8 CACHE TAGE STATIC RAM Data Retention at 2V for Battery Backup Operation Advanced CMOS Technology Low Power Operation Package Styles Available — 28 Pin 300 mil DIP — 28 Pin 300 mil Plastic SOJ Single Power Supply — 5V±10% DESCRIPTION The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% powe
P4C174 Datasheet
