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PACE1753 - CMOS MMU/COMBO

General Description

The PACE1753 (COMBO) is a support chip for the PACE1750A/AE microprocessor family.

Key Features

  • Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. System performance and device count are optimized when used with the PACE1754 Processor Interface Ci.

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Datasheet Details

Part number PACE1753
Manufacturer PYRAMID
File Size 183.21 KB
Description CMOS MMU/COMBO
Datasheet download datasheet PACE1753 Datasheet

Full PDF Text Transcription for PACE1753 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for PACE1753. For precise diagrams, and layout, please refer to the original PDF.

PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. Al...

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hitecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. System performance and device count are optimized when used with the PACE1754 Processor Interface Circuit (PIC).