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Panasonic Electronic Components Datasheet

MIP5510MS Datasheet

Silicon MOS FET

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MIP5510MS
Silicon MOS FET type integrated circuit
Features
Worldwide input voltage, 80 VAC to 280 VAC
Typical LED peak current: 0.5 A
(Peak current can be adjusted in two-stage corresponding to the input voltage.)
Dimmer control function: EX-pin voltage range, 0 V to 3 V
Function to set input voltage that can be driven: L-pin voltage range
Over temperature protection for IPD (Auto-restart)
Applications
LED-lighting, HB-LED drive circuit
Absolute Maximum Ratings Ta = 25°C±3°C
Parameter
Symbol Rating
Unit
DRAIN voltage
VD - 0.3 to +700 V
VIN voltage
VIN - 0.3 to +440 V
Input DC supply voltage
VINDC
440
V
VDD voltage
VDD - 0.3 to +7.0 V
LINE SENSE Pin voltage
VL - 0.3 to +6.0 V
External dimmer control pin voltage
VEX - 0.3 to +6.0 V
Output peak current *
IDP 1.1
A
Channel temperature
Tch 150
°C
Storage temperature
Tstg -55 to +150 °C
Operating ambient temperature
Top -40 to +80 °C
Note) *: Leading edge blanking delay: ton(BLK) + Peak current limit delay: td(OCL)
Block Diagram
VDD
REGURATOR
Package
Code
DIP7-A1
Pin Name
1. VDD
2. EX
3. L
4. VIN
5. DRAIN
6. N.C.
7. SOURCE
8. SOURCE
Marking Symbol: MIP551
VIN DRAIN
LLine-sense)
LINE SENSE
UV/OV
CL
OSCILLATOR
MAX DUTY
CLOCK
VDD UNDER
VOLTAGE
THERMAL SHUTDOWN
ENABLE
LOGIC
GATE DRIVER
SQ
R
LEADING EDGE
BLANKING
EX
PEAK CURRENT
ADJUST
CURRENT LIMIT
COMPARATER
Publication date: October 2011
Ver. AEF
SOURCE
1


Panasonic Electronic Components Datasheet

MIP5510MS Datasheet

Silicon MOS FET

No Preview Available !

MIP5510MS
Electrical Characteristics Ta = 25°C±3°C
Parameter
Symbol
Conditions
Control functions
Output frequency
Skip mode output frequency *
Maximum duty cycle
fosc
fskip
MAXDC
VDD = VDD(ON) + 0.2 V, VD = 5 V,
VL = 1.5 V, VEX = 0 V
VDD = VDD(ON) + 0.2 V, VL = 1.5 V, 
PW(on) < 350 ns
VDD = VDD(ON) + 0.2 V, VD = 5 V,
VL = 1.5 V, VEX = 0 V
VDD pin voltage
VDD(ON) VD = 5 V , VL = 1.5 V, VEX = 0 V
VDD under voltage lockout threshold
VUV VD = 5 V , VL = 1.5 V, VEX = 0 V
Operating current under non-switching
Operating current under switching
VDD pin charge current
IDD(OFF)
VDD = VDD(ON) + 0.2 V, VD = 5 V,
VL = 0 V, VEX = 0 V
IDD(ON)
VDD = VDD(ON) + 0.2 V, VD = 5 V,
VL = 1.5 V, VEX = 0 V
Ich1
VDD = 0 V, VIN = 40 V, VL = 0 V,
VEX = 0 V
Ich2
VDD = 4 V, VIN = 40 V, VL = 0 V,
VEX = 0 V
L pin line-under voltage threshold
VL(uv)
VDD = VDD(ON) + 0.2V, VD = 5 V,
VEX = 0 V *Fig. 1
L pin line-over voltage threshold
L pin voltage threshold for ILIMITL
Peak current limit
Peak current limit over VL(cll)
Peak current limit at VEX = 2.0 V *
Peak current limit reduction slope *
EX pin voltage at operation stop
VEX(off) hysteresis voltage *
Note) *: Design guaranteed item
VL(ov)
VL(cll)
ILIMIT
ILIMITL
IEX2
SLPIL
VEX(off)
VEX(hys)
VDD = VDD(ON) + 0.2V, VD = 5 V,
VEX = 0 V *Fig. 1
VDD = VDD(ON) + 0.2V, VD = 5 V,
VEX = 0 V *Fig. 1
VDD = VDD(ON) + 0.2 V, VL = 1.5 V,
VEX = 0 V *Fig. 1, 3
VDD = VDD(ON) + 0.2 V, VL = 2.5 V,
VEX = 0 V *Fig. 1
VDD = VDD(ON) + 0.2 V, VL = 1.5 V,
VEX=2.0 V *Fig. 2
VDD = VDD(ON) + 0.2 V, VL = 1.5 V,
SLPIL = (Ilimit (at EX = 1 V) - IEX2) /
((1-2)*ILIMIT) *Fig. 2
VDD = VDD(ON) + 0.2 V,
VL = 1.5 V *Fig. 2
VDD = VDD(ON) + 0.2 V,
VL = 1.5 V *Fig. 2
Min Typ Max Unit
35.2 44 52.8 kHz
0.4 ×
fosc
0.5 ×
fosc
0.625 ×
fosc
kHz
46 52 58 %
5.3 5.8 6.4 V
4.6 5.1 5.7 V
0.3 0.6 0.85 mA
0.4 0.8 1.2 mA
2.3 3.2 4.2 mA
1.0 1.9 2.6 mA
0.456 0.57 0.685 V
0.15 V
3.36 4.2 5.04 V
1.68 2.1 2.52 V
0.45 0.5 0.55 A
0.88 × 0.93 × 0.98 ×
ILIMIT ILIMIT ILIMIT
A
0.174 0.2 0.226 A
-30 %/V
2.55 2.85 3.15 V
50 mV
2 Ver. AEF


Part Number MIP5510MS
Description Silicon MOS FET
Maker Panasonic
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