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Peregrine Semiconductor

PE3339 Datasheet Preview

PE3339 Datasheet

Integer-N PLL

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Product Description
Peregrine’s PE3339 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE3339 makes
it ideal for applications such as wireless local loop
basestations, LMDS systems and other demanding
terrestrial systems.
The PE3339 features a 10/11 dual modulus prescaler,
counters, phase detector and a charge pump as shown
in Figure 1. Counter values are programmable through a
three wire serial interface.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE3339 offers excellent
RF performance with the economy and integration of
conventional CMOS.
PRODUCT SPECIFICATION
PE3339
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Internal phase detector with
charge pump
Serial programmable
Low power 23 mA at 3 V
Ultra-low phase noise
Available in 20-lead TSSOP
Figure 1. Block Diagram
www.DataSheet4UFF.ciinnom
Prescaler
10/11
Sdata
Primary
20-bit
Latch 20
Secon-
dary
20-bit
Latch
20
20
fr
Main
Counter
13
66
R Counter
PD_U
Phase
Detector
PD_D
Charge
Pump
CP
PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com
Copyright © Peregrine Semiconductor Corp. 2004
Page 1 of 12




Peregrine Semiconductor

PE3339 Datasheet Preview

PE3339 Datasheet

Integer-N PLL

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Figure 2. Pin Configuration
VDD 1
Enh 2
S_WR 3
Sdata 4
Sclk 5
GND 6
FSELS 7
E_WR 8
VDD 9
Fin 10
20 fr
19 GND
18 N/C
17 CP
16 VDD
15 Dout
14 LD
13 Cext
12 GND
11 Fin
PE3339
Advance Information
Table 1. Pin Descriptions
Pin No. Pin Name Type
1 VDD (Note 1)
2 Enh Input
3 S_WR
4 Sdata
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6 GND
7 FSELS
Input
Input
Input
Input
8
E_WR
Input
9 VDD
10 Fin
(Note 1)
Input
11 Fin
Input
12 GND
13 Cext
Output
14 LD
Output,
OD
15 Dout Output
16 VDD
(Note 1)
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kpull-up
resistor.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
Ground.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 kpull-down resistor.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 kpull-down resistor.
Same as pin 1.
Prescaler input from the VCO. Max frequency input is 3.0 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 resistor to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kseries resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
Copyright © Peregrine Semiconductor Corp. 2004
File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS
Page 2 of 12


Part Number PE3339
Description Integer-N PLL
Maker Peregrine Semiconductor
Total Page 12 Pages
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