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Peregrine Semiconductor

PE4308 Datasheet Preview

PE4308 Datasheet

RF Digital Attenuator

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Product Description
The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 75-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4308 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4308 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
RF Input
Switched Attenuator Array
RF Output
Product Specification
PE4308
75 Ω RF Digital Attenuator
5-bit, 31 dB, DC 4.0 GHz
Features
Attenuation: 1 dB steps to 31 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
75 Ω impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Figure 2. Package Type
20 Lead 4x4 mm QFN
Parallel Control 5
Serial Control 3
Power-Up Control 2
Control Logic Interface
Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V
Parameter
Test Conditions
Frequency
Minimum
Operation Frequency
Insertion Loss2
DC ≤1.2 GHz
DC
-
Attenuation Accuracy
Any Bit or Bit
Combination
DC ≤1.2 GHz
-
1 dB Compression3,4
Input IP31,2,4
Return Loss
Two-tone inputs up to
+18 dBm
1 MHz ≤1.2 GHz
1 MHz ≤1.2 GHz
DC ≤1.2 GHz
30
-
10
Switching Speed
50% control to 0.5 dB
of final value
-
Notes: 1. Device Linearity will begin to degrade below 1 MHz
2. See figures on Pages 4 to 6 for data across frequency.
3. Note Absolute Maximum in Table 3.
4. Measured in a 50 Ω system.
Typical
1.4
-
34
52
13
-
Maximum
2000
1.95
±(0.2 + 4% of atten setting)
Not to Exceed +0.4 dB
-
-
-
1
Units
MHz
dB
dB
dB
dBm
dBm
dB
s
Document No. 70-0162-04 www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
Page 1 of 11




Peregrine Semiconductor

PE4308 Datasheet Preview

PE4308 Datasheet

RF Digital Attenuator

No Preview Available !

PE4308
Product Specification
Figure 14. Pin Configuration (Top View)
C16 1
RF1 2
Data 3
Clock 4
LE 5
20-lead
QFN
4x4mm
Exposed Solder Pad
15 C8
14 RF2
13 P/S
12 Vss/GND
11 GND
Table 2. Pin Descriptions
Pin Pin
No. Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
C16
RF1
Data
Clock
LE
VDD
PUP1
PUP2
VDD
GND
GND
Vss/GND
P/S
RF2
C8
C4
C2
GND
C1
N/C
GND
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
No connect
Ground for proper operation
Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
VI
TST
PIN
VESD
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
-0.3 4.0
-0.3
VDD+
0.3
-65 150
V
V
°C
+30 dBm
500 V
Table 4. Operating Ranges
Parameter
VDD Power Supply
Voltage
IDD Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Min Typ Max Units
2.7 3.0 3.3
V
0.7xVDD
100
0.3xVDD
1
μA
V
V
μA
Input Power
+24 dBm
Temperature range
-40
85 °C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4308 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0162-04 UltraCMOS™ RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com


Part Number PE4308
Description RF Digital Attenuator
Maker Peregrine Semiconductor
Total Page 11 Pages
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