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PI6LC4820 - Ethernet Network Clock Generator

Description

The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications.

Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate the 156.25MHz outputs.

Features

  • ÎÎ3.3V supply voltage ÎÎCrystal input: 25 MHz ÎÎDifferential input: 25MHz, 156.25 MHz ÎÎOutput frequencies of 312.5, 156.25, 125MHz supported ÎÎ9 LVPECL or LVDS bank selectable outputs ÎÎLow 1ps max integrated phase noise design (12kHz to 20MHz) ÎÎOptional xtal or clock input selection ÎÎPLL Bypass mode for test ÎÎPower supply noise rejection: -50 dBc typical @ 156.25 MHz ÎÎPackaging (Pb-free & Green): 48-lead 7×7mm TQFN.

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Datasheet preview – PI6LC4820

Datasheet Details

Part number PI6LC4820
Manufacturer Pericom Semiconductor
File Size 734.94 KB
Description Ethernet Network Clock Generator
Datasheet download datasheet PI6LC4820 Datasheet
Additional preview pages of the PI6LC4820 datasheet.

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Full PDF Text Transcription

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PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features ÎÎ3.3V supply voltage ÎÎCrystal input: 25 MHz ÎÎDifferential input: 25MHz, 156.25 MHz ÎÎOutput frequencies of 312.5, 156.25, 125MHz supported ÎÎ9 LVPECL or LVDS bank selectable outputs ÎÎLow 1ps max integrated phase noise design (12kHz to 20MHz) ÎÎOptional xtal or clock input selection ÎÎPLL Bypass mode for test ÎÎPower supply noise rejection: -50 dBc typical @ 156.25 MHz ÎÎPackaging (Pb-free & Green): 48-lead 7×7mm TQFN Description The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate the 156.25MHz outputs.
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