74HC109
74HC109 is Dual JK flip-flop manufactured by Philips Semiconductors.
FEATURES
- J, K inputs for easy D-type flip-flop
- Toggle flip-flop or “do nothing” mode
- Output capability: standard
- ICC category: flip-flops GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT109
(SD) and reset (RD) inputs; also plementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n CP to n Q, n Q n SD to n Q, n Q n RD to n Q, n Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC
- 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CL = 15 p F; VCC = 5 V 15 12 12 75 3.5 20 17 14 15 61 3.5 22 ns ns ns MHz p F p F CONDITIONS HC HCT UNIT
1997 Nov 25
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
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