74HC7731 Datasheet | Philips Semiconductors

FEATURES - Frequency range DC to 100 MHz. - Separate serial data inputs - Cascadable - Functionally patible with HEF 4731 - Includes recycling mode - Direct shift out - Output capability: Standard - ICC category: LSI. APPLICATIONS - Data storage - Delay line. GENERAL DESCRIPTION The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in pliance with JEDEC standard no. 7A. The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs Da to Dd, clock inputs CPa to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC input is LOW external data can be shifted in. CI CPD Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. 74HC/HCT7731 TYP. SYMBOL t PHL/t PLH fmax PARAMETER propagation delay CPa-d to Qa-d maximum clock frequency input capacitance power dissipation capacitance per register notes 1, 2 and 3 CONDITIONS HC CL = 15 p F; VCC = 5 V 15 HCT 20 ns MHz p F p F UNIT 100 100 3.5 58 3.5 61 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz. fo = output frequency in MHz. VCC = supply voltage in V. CL = output load capacitance in p F. Ipull-up = pull-up currents in µA. 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V. 3. See also power dissipation information. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7731N 74HC/HCT7731D PACKAGE PINS 16 16 PIN POSITION DIL SO16...