• Part: 74HCT112
  • Description: Dual JK flip-flop
  • Manufacturer: Philips Semiconductors
  • Size: 106.77 KB
Download 74HCT112 Datasheet PDF
Philips Semiconductors
74HCT112
74HCT112 is Dual JK flip-flop manufactured by Philips Semiconductors.
FEATURES - Asynchronous set and reset - Output capability: standard - ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual n J, n K, clock (n CP), set (n SD) and reset (n RD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT112 The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. A HIGH level at the clock (n CP) input enables the n J and n K inputs and data will be accepted. The n J and n K inputs control the state changes of the flip-flops as shown in the function table. The n J and n K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the HIGH-to-LOW transition of n CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay n CP to n Q, n Q n SD to n Q, n Q n RD to n Q, n Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 17 15 18 66 3.5 27 19 15 19 70 3.5 30 ns ns ns MHz p F p F HCT UNIT 1998 Jun 10 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger ORDERING INFORMATION TYPE NUMBER 74HC112D; 74HCT112D...