* Input levels:
* For 74HC112: CMOS level
* For 74HCT112: TTL level
* Asynchronous set and reset
* Specified in compliance with JEDEC standard no. 7A
* ESD protection:
* HBM JESD22-A114F exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V
74HCT112 Datasheet (262.50 KB)
74HCT112
262.50 KB
Dual jk flip-flop.
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 4
* 11 January 2021
Product data sheet
1. General descr.
📁 Related Datasheet
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INTEGRATED CIRCUITS
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For a plete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 .
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