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74LV107 - Dual JK flip-flop

Description

The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107.

The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

Features

  • Wide operating: 1.0 to 5.5 V.
  • Optimized for low voltage.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 FEATURES • Wide operating: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Output capability: standard • ICC category: flip-flops QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.
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