74LV109 flip-flop equivalent, dual jk flip-flop.
* Optimized for low voltage applications: 1.0 to 3.6 V
* Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
* Typical VOLP (output ground bounce) <.
1.0 to 3.6 V
* Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
* Typical VOLP (output ground bounc.
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LV109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs.
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