* - Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5) - Vdd=Vddq=2.6V+0.1V (for speed grade -5) - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transit
A3S12D30ETP Datasheet (2.10 MB)
A3S12D30ETP
Powerchip
2.10 MB
512mb ddr sdram.
512Mb DDR SDRAM Specification A3S12D30ETP A3S12D40ETP Powerchip Semiconductor Corp. No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu Taiwan.
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