ASM2P5T905A Datasheet 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

Manufacturer: PulseCore

ASM2P5T905A 2.5v single data rate 1:5 clock buffer terabuffer by PulseCore - Datasheet Preview

Datasheet Details

Part number	ASM2P5T905A
Manufacturer	PulseCore
File Size	677.83 KB
Description	2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Download	ASM2P5T905A Download (PDF)

General Description

The ASM2P5T905A 2.5V single data rate (SDR) Clock buffer is a user-selectable single-ended or differential input Block Diagram TxS to five single-ended outputs buffer built on advanced metal CMOS technology.

The SDR Clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network.

The ASM2P5T905A can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs.

Overview

November 2006 rev 0.2 ASM2P5T905A 2.5V Single Data Rate 1:5 Clock Buffer.

Key Features

Guaranteed Low Skew < 25pS (max).
Very low duty cycle distortion.
High speed propagation delay < 2.5nS. (max).
Up to 250MHz operation.
Very low CMOS power levels.
1.5V VDDQ for HSTL interface.
Hot insertable and Over-voltage tolerant inputs.
3 level inputs for selectable interface.
Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or.

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