HYI25D256800C Overview
March 2007 HYB25D256[40/80/16]0CE(L) HYB25D256[40/80/16]0C[T/C/F] HYI25D256[80/16]0C[C/E/F/T] .. 256-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS pliant or Lead-Containing Internet Data Sheet Rev. 72 85, 86 Subjects (major changes since last revision) Adapted internet edition Corrected table 7 mode register definition Changed the 1.1 mA to 1.5 mA for low power Changed the ball size from 0.460 mm to 0.450 mm Previous...
HYI25D256800C Key Features
- +70 °C) or Industrial Temperature Range (-40 °C
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst Lengths: 2, 4, or 8