HYI25D512160C Datasheet | Qimonda

Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. - - - - - - - - - - - - - - - - - - Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions mands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported t RAP= t RCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 patible) I/O VDDQ = 2.5 V ± 0.2 V VDD = 2.5 V ± 0.2 V Packages : P-TSOPII-66, PG-TSOPII-66, P-TFBGA-60, PG-TFBGA-60 TABLE 1 Performance for - 5 and - 6 Part Number Speed Code Speed Grade Max. Clock Frequency ponent @CL3 @CL2.5 @CL2 - 5 DDR400B - 6 DDR333B 166 166 133 Unit - MHz MHz MHz f CK3 f CK2.5 f CK2 200 166 133 Rev. 1.0, 2006-11 11082006-S9OT-UFSN Internet Data Sheet HYI25D512160C[C/E/F/T] 512-Mbit Double-Data-Rate SDRAM Description Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active mand, which is then followed by a Read or Write mand. The address bits registered coincident with the Active mand are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write mand are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of...