HYI25D256800C
HYI25D256800C is 256-Mbit Double-Data-Rate SDRAM manufactured by Qimonda.
- Part of the HYI25D256160C comparator family.
- Part of the HYI25D256160C comparator family.
Overview
Features
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- Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported t RAP = t RCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 patible) I/O VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400) VDD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400) Standard Temperature Range (0 °C
- +70 °C) or Industrial Temperature Range (- 40 °C
- +85 °C) P-TFBGA-60-12 package with 3 depopulated rows (8 × 12 mm2) P-TSOPII-66 package Ro HS1) pliant product types available (green product)
This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information.
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Burst Lengths: 2, 4, or 8
- CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
TABLE 1
Performance of
- 5,
- 6 and
- 7
Product Type Speed Code Speed Grade Max. Clock Frequency ponent @CL3 @CL2.5 @CL2
- 5 DDR400B
- 6 DDR333B 166 166 133
- 7 DDR266A
- 143 133 Unit
- MHz MHz MHz f CK3 f CK2.5 f CK2
200 166 133
1) Ro HS pliant Product: Restriction of the use of certain hazardous substances (Ro HS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council...
