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Ramtron

FM25L512 Datasheet Preview

FM25L512 Datasheet

3V F-RAM Memory

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www.DataSheet.co.kr
Preliminary
FM25L512
512Kb FRAM Serial 3V Memory
Features
512K bit Ferroelectric Nonvolatile RAM
Organized as 65,536 x 8 bits
Unlimited Read/Write Cycles
10 Year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
Up to 20 MHz Frequency
Direct Hardware Replacement for EEPROM
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Write Protection Scheme
Hardware Protection
Software Protection
Low Power Consumption
Low Voltage Operation 3.0V – 3.6V
20 µA Standby Current
Industry Standard Configurations
Industrial Temperature -40°C to +85°C
8-pin “Green”/RoHS TDFN Package
Footprint Compatible with SOIC-8 (see pg 12)
Description
The FM25L512 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25L512 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25L512 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L512 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L512 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Aug. 2007
Pin Configuration
Top View
/CS 1
SO 2
8 VDD
7 /HOLD
/WP 3
VSS 4
6 SCK
5 SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (3.0 to 3.6V)
Ground
Ordering Information
FM25L512-DG 8-pin “Green”/RoHS TDFN
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
Datasheet pdf - http://www.DataSheet4U.net/




Ramtron

FM25L512 Datasheet Preview

FM25L512 Datasheet

3V F-RAM Memory

No Preview Available !

www.DataSheet.co.kr
WP
CS
HOLD
SCK
SI
Instruction Decode
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
16
8192 x 64
FRAM Array
8
Data I/O Register
3
Nonvolatile Status
Register
FM25L512
SO
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
SCK Input
/HOLD
Input
/WP Input
SI Input
SO Output
VDD
VSS
Supply
Supply
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register
only. A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (3.0V to 3.6V)
Ground
Rev. 1.2
Aug. 2007
Page 2 of 13
Datasheet pdf - http://www.DataSheet4U.net/


Part Number FM25L512
Description 3V F-RAM Memory
Maker Ramtron
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