* 128K x 36 memory configurations
* Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access)
* ZBTTM Feature - No dead cycles between wr.

* 4-word burst capability (interleaved or linear)
* Individual byte write (BW1 - BW4) control (May tie active) .

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zer.

71V2556SA

71V256SA

71V016SA

71V416

71V416L

71V416S

71V424L

71V424S

7100MD9AV2BE

7100MD9AV2QE

71016

71016S

7101MD9AV2BE