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Renesas Electronics Components Datasheet

83054 Datasheet

Single-Ended Multiplexer

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4:1, Single-Ended Multiplexer
83054
Data Sheet
GENERAL DESCRIPTION
The 83054 is a low skew, 4:1, Single-ended Multiplexer and a
member of the family of High Performance Clock Solutions from IDT.
The 83054 has four selectable single-ended clock inputs and one
single-ended clock output. The output has a V pin which may be
DDO
set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage
translation applications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug purposes. The device operates up to 250MHz and is pack-
aged in a 16 TSSOP package.
FEATURES
• 4:1 single-ended multiplexer
• Q nominal output impedance: 7Ω (V = 3.3V)
DDO
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), V = V = 3.3V
DD
DDO
• Input skew: 225ps (maximum), V = V = 3.3V
DD
DDO
• Part-to-part skew: 780ps (maximum), V = V = 3.3V
DD
DDO
• Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V
• Operating supply modes:
V /V
DD DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK0
CLK1
CLK2
CLK3
SEL1
SEL0
OE
PIN ASSIGNMENT
Q
83054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
©2015 Integrated Device Technology, Inc
1
December 15, 2015


Renesas Electronics Components Datasheet

83054 Datasheet

Single-Ended Multiplexer

No Preview Available !

83054 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
3
4, 8,
10, 14
OE
CLK3, CLK2,
CLK1, CLK0
Input
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
5
GND
Power
Power supply ground.
7, 9
SEL1, SEL0
Input
Pulldown
Clock select input. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
2, 6, 11, 13, 15
nc
Unused
No connect.
12
V
Power
Power and input supply pin.
DD
16
V
Power
Output supply pin.
DDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
R
Output Impedance
OUT
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
SEL1
SEL0
0
0
0
1
1
0
1
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
©2015 Integrated Device Technology, Inc
2
December 15, 2015



Part Number 83054
Description Single-Ended Multiplexer
Maker Renesas
Total Page 3 Pages
PDF Download

83054 Datasheet PDF





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