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83115 Datasheet

1-TO-16 LVCMOS/LVTTL Fanout Buffer

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Low Skew, 1-TO-16 LVCMOS/LVTTL
Fanout Buffer
83115
DATA SHEET
General Description
The 83115 is a low skew, 1-to-16 LVCMOS/ LVTTL Fanout Buffer
from IDT. The 83115 single-ended clock input accepts LVCMOS or
LVTTL input levels. The 83115 operates at full 3.3V supply mode
over the commercial temperature range. Guaranteed output and
part-to-part skew characteristics make the 83115 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
Features
Sixteen LVCMOS / LVTTL outputs, 15output impedance
One LVCMOS / LVTTL clock input
Maximum output frequency: 200MHz
All inputs are 5V tolerant
Output skew: 250ps (maximum)
Part-to-part skew: 800ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
Full 3.3V operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE2
VDD
4
IN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE1
4
GND
OE0
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Pin Assignment
OE1 1
Q0 2
Q1 3
Q2 4
VDD 5
VDD 6
Q3 7
Q4 8
GND 9
GND 10
Q5 11
Q6 12
Q7 13
IN 14
28 OE2
27 Q15
26 Q14
25 Q13
24 VDD
23 VDD
22 Q12
21 Q11
20 GND
19 GND
18 Q10
17 Q9
16 Q8
15 OE0
83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.5mm package body
R Package
Top View
83115 Rev C 3/20/15
1
©2015 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

83115 Datasheet

1-TO-16 LVCMOS/LVTTL Fanout Buffer

No Preview Available !

83115 DATA SHEET
Table 1. Pin Descriptions
Number
1
2, 3, 4, 7, 8,
11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
5, 6, 23, 24
9, 10, 19, 20
14
15
Name
OE1
Q0, Q1, Q2, Q3,
Q4, Q5, Q6,
Q7, Q8, Q9,
Q10, Q11, Q12,
Q13, Q14, Q15
VDD
GND
IN
OE0
28
OE2
Type
Input
Pullup
Description
Output enable pin. When LOW, forces outputs Q[2:7] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
Output
Single-ended clock outputs. 15output impedance.
LVCMOS/LVTTL interface levels.
Power
Power
Input
Input
Input
Pulldown
Pullup
Pullup
Positive supply pins.
Power supply ground.
Single-ended clock input. 5V tolerant. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, forces outputs Q[8:13] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
Output enable pin. When LOW, forces outputs Q[0:1] and Q[14:15] to
Hi-Z state. 5V tolerant. LVCMOS/LVTTL interface levels.
See Table 3.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output); NOTE 1
ROUT
Output Impedance
Test Conditions
VDD = 3.465V
VDD = 3.3V
Minimum
Typical
4
51
51
11
15
Maximum
Units
pF
k
k
pF
Rev C 3/20/15
2
LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER



Part Number 83115
Description 1-TO-16 LVCMOS/LVTTL Fanout Buffer
Maker Renesas
Total Page 3 Pages
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83115 Datasheet PDF





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