Datasheet4U Logo Datasheet4U.com

894D115I-01 - Clock/Data Recovery

Description

The 894D115I-01 is a clock and data recovery circuit.

The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal.

The output signals of the device are the recovered clock and retimed data signals.

Features

  • Clock recovery for STM-4 (OC-12/STS-12) and STM-1 (OC-3/STS-3).
  • Input: NRZ data (622.08 or 155.52 Mbit/s).
  • Output: clock signal (622.08MHz or 155.52MHz) and retimed data signal at 622.08 or 155.52 Mbit/s.
  • Internal PLL for clock generation and clock recovery.
  • Differential inputs can accept LVPECL levels.
  • Differential LVPECL data and clock outputs.
  • Lock reference input and PLL lock output.
  • 19.44MHz reference clock input.

📥 Download Datasheet

Datasheet preview – 894D115I-01

Datasheet Details

Part number 894D115I-01
Manufacturer Renesas
File Size 390.76 KB
Description Clock/Data Recovery
Datasheet download datasheet 894D115I-01 Datasheet
Additional preview pages of the 894D115I-01 datasheet.

📁 Similar Datasheet

Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device 894D115I-01 DATA SHEET General Description The 894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals. Input and output are differential signals for best signal integrity and to support high clock and data rates. All control inputs and outputs are single-ended signals. An internal PLL is used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock recovery PLL and to provide a clock reference in the absence of serial input data.
Published: |