8A34004
Key Features
- Two independent timing channels
- Each can act as a frequency synthesizer, jitter attenuator, Digitally Controlled Oscillator (DCO), or Digital Phase Lock Loop (DPLL)
- DPLLs generate tele pliant clocks pliant with ITU-T G.8262 for Synchronous Ethernet pliant with legacy SONET/SDH and PDH requirements
- DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 12µHz to 22kHz
- DPLL/DCO channels share frequency information using the bo Bus to simplify pliance with ITU-T G.8273.2
- Generates output frequencies that are independent of input frequencies via a Fractional Output Divider (FOD)
- Each FOD supports output phase tuning with 1ps resolution 4 Differential / 8 LVCMOS outputs
- Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
- Jitter below 150fs RMS (10kHz to 20MHz)
- LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes supported
