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9DBV0431 Datasheet

Zero-delay/Fanout Buffer

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4-output 1.8V PCIe Gen1-2-3
Zero-delay/Fanout Buffer (ZDB/FOB)
9DBV0431
DATASHEET
Description
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
53mW typical power consumption in PLL mode; minimal
power consumption
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBV0431 REVISION E 04/28/16
1
©2016 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

9DBV0431 Datasheet

Zero-delay/Fanout Buffer

No Preview Available !

9DBV0431 DATASHEET
Pin Configuration
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
FB_DNC# 3
VDDR1.8 4
CLK_IN 5
CLK_IN# 6
GNDR 7
GNDDIG 8
32 31 30 29 28 27 26 25
9DBV0431
epad is Gnd
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.8
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus OEx# Pin
DIFx
PLL
OEx bit
True O/P Comp. O/P
0
X
X
X
Low
Low
Off
1
Running
0
X
Low
Low
On1
1
Running
1
0
Running
Running
On1
1
Running
1
1
Low
Low
On1
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
Pin Number
VDD
GND
4
7
9
8
16, 25
15,20,26,30
21
20
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 2
REVISION E 04/28/16



Part Number 9DBV0431
Description Zero-delay/Fanout Buffer
Maker Renesas
Total Page 3 Pages
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9DBV0431 Datasheet PDF





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