9DBV0431 Key Features
- 1-200Hz Low-Power (LP) HCSL DIF pairs
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew <50ps
- DIF additive phase jitter is <100fs rms for PCIe Gen3
- DIF additive phase jitter <300fs rms for 12k-20MHz
- LP-HCSL outputs save 8 resistors; minimal board space
- 53mW typical power consumption in PLL mode; minimal
- OE# pins; support DIF power management
- HCSL patible differential input; can be driven by
- Programmable output amplitude; allows tuning for various
