9QXL2001C Datasheet - Renesas

PCIe Clock Buffer

9QXL2001C Features

* ▪ 8 OE# pins provide hardware control of 8 outputs ▪ SMBus allows software control of each output ▪ 25MHz Side-Band Interface allows real-time control of all 20 outputs ▪ Outputs remain Low/Low when powered up with floating input clock ▪ Power Down Tolerant (PDT) inputs ▪ 85Ω Low-Power HCSL (LP-HCSL

9QXL2001C General Description

The 9QXL2001C is an enhanced-performance 9QXL2001B with ultra-low-additive phase jitter for PCIe Gen5, Gen6 and UPI applications. The 9QXL2001C also reduces propagation delay by approximately 50% with respect to the 9QXL2001B. PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference.

9QXL2001C Datasheet (903.05 KB)