Datasheet4U Logo Datasheet4U.com

HD74HC73 - Dual J-K Flip-Flops

Description

The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs.

Clear is independent of the clock and accomplished by a low level on the input.

Features

  • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC73P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74HC73FPEL SOP-14 pin (JEITA) PRSP0014DF-B.

📥 Download Datasheet

Datasheet preview – HD74HC73

Datasheet Details

Part number HD74HC73
Manufacturer Renesas
File Size 225.10 KB
Description Dual J-K Flip-Flops
Datasheet download datasheet HD74HC73 Datasheet
Additional preview pages of the HD74HC73 datasheet.

📁 Similar Datasheet

  • HD74HC73 - Dual J-K Flip-Flops (with Clear) (Hitachi Semiconductor)
  • HD74HC74 - Dual D-type Flip-Flops (with Preset and Clear) (Hitachi Semiconductor)
  • HD74HC75 - Quad. Bistable Latches (Hitachi Semiconductor)
  • HD74HC76 - Dual J-K Flip-Flops (with Preset and Clear) (Hitachi Semiconductor)
  • HD74HC77 - 4-bit Bistable Latch (Hitachi Semiconductor)
  • HD74HC78 - Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock) (Hitachi Semiconductor)
  • HD74HC00 - Quad. 2-input NAND Gates (Hitachi Semiconductor)
  • HD74HC01 - Quad. 2-input NAND Gates (Hitachi Semiconductor)
  • HD74HC02 - Quad. 2-input NOR Gates (Hitachi Semiconductor)
  • HD74HC04 - Hex Inverters (Hitachi Semiconductor)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
HD74HC73 Dual J-K Flip-Flops (with Clear) REJ03D0548-0200 (Previous ADE-205-420) Rev.2.00 Oct 06, 2005 Description The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input.
Published: |