ICS667-01 Datasheet | Renesas

Description The ICS667-01 is a low-cost, low jitter, high-performance PLL clock synthesizer designed to produce the 74.176 MHz clock necessary for HDTV systems. Using IDT’s patented analog Phase-Locked Loop (PLL) techniques, the device accepts a 27 MHz crystal or clock input. The zero ppm synthesis error exactly locks the display to the digital stream. IDT manufactures the largest variety multimedia clock synthesizers for all applications. Consult IDT to eliminate crystals and oscillators from your board. Features - Packaged in 8-pin SOIC - Pb (lead) free package, Ro HS pliant - Input frequency of 27 MHz - Zero ppm synthesis error in output clock - 3.3 V ±5% operating supply - Ideal for HDTV applications and oscillator manufacturers - Advanced, low power, sub-micron CMOS process Block Diagram 27 MHz crystal or clock input ICLK/X1 X2 Clock Buffer Optional tuning crystal capacitors VDD OE Clock Synthesis and Control Circuitry 2 GND CLK 74.17582418 MHz 27.0000 MHz IDT™ / ICS™ HDTV CLOCK SYNTHESIZER ICS667-01 REV E 051310 ICS667-01 HDTV CLOCK SYNTHESIZER CLOCK SYNTHESIZER Pin Assignment ICLK/X1 VDD GND CLK 1 2 3 4 8 X2 7 27M 6 OE 5 GND Pin Descriptions Pin Pin Number Name 1 ICLK/X1 2 VDD 3 GND 4 CLK 5 GND 6 OE 7 27M 8 X2 Pin Type XI Power Power Output Power Input Output Pin Description Crystal connection. Connect to a 27 MHz fundamental crystal or clock. Connect to +3.3 V. Connect to ground. 74.17582418 MHz. Connect to ground. Output enable. Tri-states CLK output when low. Internal pull-up to VDD. 27 MHz buffered clock or crystal oscillator output. Crystal connection. Connect to a 27 MHz crystal, or leave unconnected for clock input. External ponents Decoupling...