ICS671-03 Datasheet | Renesas

3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description The ICS671-03 is a low phase noise, high speed PLL based, 8 output, low skew zero delay buffer. Based on IDT’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin. Block Diagram Features - Packaged in 16 pin narrow (150 mil) SOIC - Clock outputs from 10 to 133 MHz - Zero input-output delay - Eight low-skew (<200 ps) outputs - Device-to-device skew <700 ps - Low jitter (<200 ps) - Full CMOS outputs with 25 m A output drive capability at TTL levels - 5 V tolerant FBIN and CLKIN pins - Tri-state mode for board-level testing - Advanced, low power, sub-micron CMOS process - 3.3 V operating voltage - Industrial temperature range of -40 to 85 °C - Ro HS pliant (Pb free) package IDT™ 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER ICS671-03 REV D 051310 ICS671-03 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Pin Assignment ZDB AND MULTIPLIER Output Clock Mode Select Table S2 S1 00 01 10 11 CLKA1:A4 Tri-state (note 1) Stopped Low Running Running CLKB1:B4...