Datasheet4U Logo Datasheet4U.com

ICS672-02 - QUADRACLOCK QUADRATURE DELAY BUFFER

Download the ICS672-02 datasheet PDF. This datasheet also covers the ICS672-01 variant, as both devices belong to the same quadraclock quadrature delay buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals.

Key Features

  • Packaged in 16-pin SOIC.
  • Pb (lead) free package, RoHS compliant.
  • Input clock range from 5 MHz to 150 MHz (depends on multiplier).
  • Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02).
  • Zero input-output delay.
  • Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections.
  • Four accurate (.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ICS672-01-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ICS672-02
Manufacturer Renesas
File Size 226.75 KB
Description QUADRACLOCK QUADRATURE DELAY BUFFER
Datasheet download datasheet ICS672-02 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS670-01 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER IDT
ICS670-02 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER IDT
ICS670-03 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER IDT
ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER IDT
ICS671-06 Low Skew Buffer Integrated Circuit Systems

Other Datasheets by Renesas

Part Number Description
ICS672-01 QUADRACLOCK QUADRATURE DELAY BUFFER
ICS670-01 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER
ICS670-03 LOW PHASE NOISE ZERO-DELAY BUFFER/MULTIPLIER
ICS671-01 ZERO DELAY LOW SKEW BUFFER/MULTIPLIER
ICS671-03 LOW SKEW BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
QUADRACLOCK QUADRATURE DELAY BUFFER DATASHEET ICS672-01/02 Description The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The ICS672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin.