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ICS8305I-02 Datasheet

LVCMOS-to-LVCMOS Fanout Buffer

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Low Skew, 1-to-4 Multiplexed Differential/ ICS8305I-02
LVCMOS-to-LVCMOS Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2016
DATA SHEET
General Description
The ICS8305I-02 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305I-02 has
selectable clock inputs that accept either differential or single-ended
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin. Outputs are forced LOW when
the clock is disabled. A separate output enable pin controls whether
the outputs are in the active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the
ICS8305I-02 ideal for those applications demanding well defined
performance and repeatability.
Features
Four LVCMOS/LVTTL outputs, (two banks of two LVCMOS
outputs)
Selectable differential CLK, nCLK pair or LVCMOS_CLK input
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 250MHz
Output skew: 100ps (maximum)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
For functional replacement device use 8305
Block Diagram
OEA Pullup
CLK_EN Pullup
LVCMOS_CLK Pulldown
00
CLK
nCLK
Pulldown
Pullup
11
CLK_SEL Pullup
D
Q
LE
OEB Pullup
QA0
QA1
QB0
QB1
Pin Assignment
OEA 1
OEB 2
VDD 3
CLK_EN 4
CLK 5
nCLK 6
CLK_SEL 7
LVCMOS_CLK 8
16 QA0
15 VDDO_A
14 QA1
13 GND
12 QB0
11 VDDO_B
10 QB1
9 GND
ICS8305I-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
ICS8305AGI-02 REVISION A May 6, 2016
1
©2016 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS8305I-02 Datasheet

LVCMOS-to-LVCMOS Fanout Buffer

No Preview Available !

ICS8305I-02 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
Output enable for Bank A outputs. When LOW, QAx outputs are in HIGH
1
OEA
Input
Pullup impedance state. When HIGH, QAx outputs are active. LVCMOS / LVTTL
interface levels.
Output enable for Bank B outputs. When LOW, QBx outputs are in HIGH
2
OEB
Input
Pullup impedance state. When HIGH, QBx outputs are active. LVCMOS / LVTTL
interface levels.
3
VDD
Power
Positive supply pins.
4
CLK_EN
Input
Pullup
Synchronizing clock enable. When LOW, the output clocks are disabled. When
HIGH, output clocks are enabled. LVCMOS / LVTTL interface levels.
5
CLK
Input Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup Inverting differential clock input.
7
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects CLK, nCLK inputs.
When LOW, selects LVCMOS_CLK input. LVCMOS / LVTTL interface levels.
8
LVCMOS_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
9, 13
GND
Power
Power supply ground.
10, 12
QB1, QB0
Output
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
11
14, 16
VDDO_B
QA1, QA0
Power
Output
Output supply pin for Bank B outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
15
VDDO_A
Power
Output supply pin for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
Test Conditions
VDDO_A = VDDO_B = 3.3V
VDDO_A = VDDO_B = 2.5V
VDDO_A = VDDO_B = 1.8V
VDDO_A = VDDO_B = 1.5V
Minimum
Typical
4
51
51
13
9
11
15
20
Maximum
Units
pF
k
k
pF
ICS8305AGI-02 REVISION A May 6, 2016
2
©2016 Integrated Device Technology, Inc.


Part Number ICS8305I-02
Description LVCMOS-to-LVCMOS Fanout Buffer
Maker Renesas
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