ICS98UAE877A driver equivalent, 1.5v low-power wide-range frequency clock driver.
* Low skew, low jitter PLL clock driver
* 1 to 10 differential clock distribution
* Feedback pins for input to output synchronization
* Spread Spectrum to.
* DDR2 Memory Modules / Zero Delay Board Fan Out
* Provides complete DDR DIMM solution with
IDT74SSTUAE32xxx fam.
The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels.
ICS98UAE877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differen.
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