ICS9ERS3165 Datasheet | Renesas

Features : - 2 - CPU differential low power push-pull pairs - 9 - SRC differential low power push-pull pairs - 1 - CPU/SRC selectable differential low power push-pull pair - 1 - SRC/DOT selectable differential low power push-pull pair - 5 - PCI, 33MHz - 1 - PCI_F, 33MHz free running - 1 - USB, 48MHz - 1 - REF, 14.318MHz Key Specifications: - CPU outputs cycle-cycle jitter < 85ps - SRC output cycle-cycle jitter < 125ps - PCI outputs cycle-cycle jitter < 250ps - +/- 100ppm frequency accuracy on CPU & SRC clocks Features /Benefits: - Does not require external pass transistor for voltage regulator - Integrated 33ohm series resistors on differential outputs, Zo=50Ω - Supports spread spectrum modulation, default is 0.5% down spread - Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning - Selectable between one SRC differential push-pull pair and two single-ended outputs Pin Configuration PCI0/CR#_A 1 VDDPCI 2 PCI1/CR#_B 3 PCI2/TME 4 PCI3 5 PCI4/27_SEL 6 PCI5_F/ITP_EN 7 GNDPCI 8 VDD48 9 USB48M/FSLA 10 GND48 11 VDDI/O96MHz 12 DOT96T/SRCT_LR0 13 DOT96C/SRCC_LR0 14 GND 15 VDD 16 27FIX/LCDT/SRCT_LR1/SE1 17 27SS/LCDC/SRCC_LR1/SE2 18 GND 19 VDDPLL3I/O 20 SRCT_LR2/SATACLKT 21 SRCC_LR2/SATACLKC 22 GNDSRC 23 SRCT_LR3/CR#_C 24 SRCC_LR3/CR#_D 25 VDDSRCI/O 26 SRCT_LR4 27 SRCC_LR4 28 GNDSRC 29 SRCT_LR9 30 SRCC_LR9 31 SRCC_LR11/CR#_G 32 64-TSSOP 64 SCLK 63 SDATA 62 REF/FSLC/TEST_SEL 61 VDDREF 60 X1 59 X2 58 GNDREF 57 FSLB/TEST_MODE 56 CK_PWRGD/PD# 55 VDDCPU 54 CPUT_LR0 53 CPUC_LR0 52 GNDCPU 51 CPUT_F_LR1 50 CPUC_F_LR1 49 VDDCPU_IO 48 NC 47 CPUT_ITP_LR2/SRCT8 46 CPUC_ITP_LR2/SRCC8 45 VDDSRCI/O 44 SRCT_LR7/CR#_F 43 SRCC_LR7/CR#_E 42 GNDSRC 41 SRCT_LR6 40 SRCC_LR6 39 VDDSRC 38 PCI_STOP# 37 CPU_STOP# 36 VDDSRCI/O 35 SRCC_LR10 34 SRCT_LR10 33 SRCT_LR11/CR#_H...