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ICS9FG1201H - Frequency Gearing Clock

General Description

The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification.

This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications.

The outputs are configured with two groups.

Key Features

  • Benefits.
  • Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs).
  • Power up default is all outputs in 1:1 mode.
  • DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock.
  • DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock.
  • Spread spectrum compatible.
  • Supports output clock frequencies up to 400 MHz.
  • 8 Selectable SMBus addresses.
  • SMBus address determines PLL or Bypass mode Functional Block Diagram OE# OE(9:0)#.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DATASHEET Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD ICS9FG1201H Description The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B or CK410B+ main clock generator, such as the ICS932S421, drives the ICS9FG1201.