ICS9FG1201H Overview
The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups.
ICS9FG1201H Key Features
- Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
- Power up default is all outputs in 1:1 mode
- DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock
- DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock
- Spread spectrum patible
- Supports output clock frequencies up to 400 MHz
- 8 Selectable SMBus addresses
- SMBus address determines PLL or Bypass mode
- 09/23/09
ICS9FG1201H Applications
- DIF output cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 50ps within a group
- DIF output-to-output skew < 100ps across all outputs
