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Renesas Electronics Components Datasheet

IDT23S08 Datasheet

3.3V ZERO DELAY CLOCK MULTIPLIER

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IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
IDT23S08
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT23S08-1 1x
– IDT23S08-2 1x, 2x
– IDT23S08-3 2x, 4x
– IDT23S08-4 2x
– IDT23S08-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
DESCRIPTION:
The IDT23S08 is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08 has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08 enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT23S08 is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08 is characterized for both Industrial and Commercial opera-
tion.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
PLL
REF
2
(-5)
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
(-2, -3) 2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2003 Integrated Device Technology, Inc.
MAY 2010
DSC 6394/10


Renesas Electronics Components Datasheet

IDT23S08 Datasheet

3.3V ZERO DELAY CLOCK MULTIPLIER

No Preview Available !

IDT23S08
3.3V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
REF
1
CLKA1
2
CLKA2
3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
16
FBK
15
CLKA4
14
CLKA3
13
VDD
12
GND
11 CLKB4
10
CLKB3
9
S1
SOIC/ TSSOP
TOP VIEW
PIN DESCRIPTION
REF (1)
CLKA1(2)
CLKA2(2)
VDD
GND
CLKB1(2)
CLKB2(2)
S2(3)
S1(3)
CLKB3(2)
CLKB4(2)
GND
VDD
CLKA3(2)
CLKA4(2)
FBK
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Functional Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD
VI (2)
VI
IIK (VI < 0)
IO
(VO = 0 to VDD)
VDD or GND
TA = 55°C
(in still air)(3)
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
Input Clamp Current
Continuous Output Current
–0.5 to +4.6 V
–0.5 to +5.5 V
–0.5 to
V
VDD+0.5
–50
mA
±50
mA
Continuous Current
±100
mA
Maximum Power Dissipation
0.7
W
TSTG
Operating
Temperature
Storage Temperature Range
Commercial Temperature
Range
–65 to +150 °C
0 to +70 °C
Operating
Temperature
Industrial Temperature
Range
-40 to +85 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
2



Part Number IDT23S08
Description 3.3V ZERO DELAY CLOCK MULTIPLIER
Maker Renesas
Total Page 3 Pages
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IDT23S08 Datasheet PDF





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